NO .. The Architecture of a CPLD is different of a FPGA
THE FPGA is like a chess board with every square being a"CELL"
You use a synthesis tool to design .The tools does the mapping of the logic functions in a process called routing .This is very sofisticated and complex . At the end you can generate a REPORT . That will tell you if the timings concerns are met. In a general maner you don't need to worry about the underlaying structure of the FPA .. only in very particular cases when you need to optimize the timing .. FPGA have thousands of gates .. so you are never short! On the other hand a pins can be configured as either an inpur or output or both!

CLPD are diffrent .They have some pins only inputs and some pins that are both . The pins that are inputs go through a CONNECTION MATRIX
that will be programmed by some soft either low or high level description language or schematic using "PRIMITIVES" . In CPLDs you have to be more aware of the internal architecture to get the best out of it :SPEED
But the propagation times are fixed and well known !

CPLD are better to be used when you need very fast logic requirements
like memory mapping in an address bus !